Silicon Labs /Series0 /EZR32HG /EZR32HG220F64R67 /PRS /CH5_CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CH5_CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SIGSEL 0 (NONE)SOURCESEL0 (OFF)EDSEL 0 (ASYNC)ASYNC

EDSEL=OFF, SOURCESEL=NONE

Description

Channel Control Register

Fields

SIGSEL

Signal Select

SOURCESEL

Source Select

0 (NONE): No source selected

1 (VCMP): Voltage Comparator

8 (ADC0): Analog to Digital Converter 0

16 (USART0): Universal Synchronous/Asynchronous Receiver/Transmitter 0

17 (USARTRF1): Universal Synchronous/Asynchronous Receiver/Transmitter 1

28 (TIMER0): Timer 0

29 (TIMER1): Timer 1

30 (TIMER2): Timer 2

40 (RTC): Real-Time Counter

48 (GPIOL): General purpose Input/Output

49 (GPIOH): General purpose Input/Output

54 (PCNT0): Pulse Counter 0

EDSEL

Edge Detect Select

0 (OFF): Signal is left as it is

1 (POSEDGE): A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal

2 (NEGEDGE): A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal

3 (BOTHEDGES): A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal

ASYNC

Asynchronous reflex

Links

() ()